The present invention relates to integrated circuits and, more particularly, to output drivers for use in integrated circuits.
Output drivers are typically used to drive a signal onto a bus line that has a relatively large load. For many applications, the strength of the output driver (which is related to the effective width-to-length ratio of the pull-up and pull-down devices implementing the output driver) is carefully designed to quickly drive the signal under the expected load conditions but at the same time, not too quickly so as to cause noise problems on the power buses. In an integrated circuit, several factors can affect the strength of an output driver. For example, variations in process, supply voltage and temperature (i.e., PVT) can affect the strength of the output driver, thereby creating timing and/or noise problems. In addition, the strength requirements of the output drivers of a digital or mixed signal integrated circuit may change depending on the clock frequency. For example, a circuit may use a reduced clock frequency in a power-saving mode (which tends to reduce dynamic power dissipation in the circuit). Because the lower clock frequency generally relaxes the rise and fall time requirements of the output driver, the output driver strength can be also be reduced (which also tends to reduce dynamic power dissipation) without causing additional timing problems.
Conventional output drivers may use relatively complex analog techniques and/or external elements to adjust the output driver strength. In addition, the area occupied by circuits implementing such conventional techniques tends to be relatively large. Accordingly, there is a need for an output driver that can automatically adjust its strength in response to PVT and clock frequency variations.
In accordance with aspects of the present invention, an output driver that can adjust its strength in response to PVT and clock frequency variations is provided. In one aspect of the present invention, the output driver includes an adjustable main output stage and a control circuit with a digital delay locked loop (digital DLL) circuit and an adjustable scaled output stage. The main output stage and the scaled output stage are both configured to adjust their strengths in response to a control signal generated by the control circuit. The control circuit receives a clock signal and propagates a transition (e.g., a rising edge or a falling edge) through the scaled output stage. The time required to propagate the transition through the scaled output stage is dependent on the strength of the scaled output stage. The DLL circuit compares the propagation time through the scaled output stage with a reference signal (that is dependent on the clock signal frequency) and generates the control signal as a function of comparison. In particular, the DLL circuit generates the control signal to adjust the scaled output stage strength (instead of a delay line as in a conventional DLL) so as to synchronize the propagation time with the reference signal. The main output stage, receiving the same control signal, adjusts its strength in a corresponding manner. In a further refinement, the DLL is a digital DLL.
When PVT and/or clock signal variations occur, the synchronization between the propagation time and the reference signal will be perturbed, which causes the DLL circuit to generate the control signal so as to readjust the strength of the scaled output stage so that the propagation time is again synchronized with the reference signal. The use of the DLL circuit in the control circuit allows the output driver to be less complex and smaller than conventional output drivers that use analog techniques to compensate for variations in PVT.
In accordance with another aspect of the present invention, the DLL circuit includes an up/down counter and a filter circuit to generate a digital control signal to adjust the strengths of the main and scaled output stages. For example, in one embodiment, the counter is a three-bit counter generating a three-bit digital control signal. In a further refinement, the control signal enables/disables a number of parallel pull-up/pull-down blocks (also referred to herein as xe2x80x9cfingersxe2x80x9d) that form each output stage in response to the count of the counter. For example, in one embodiment the most significant bit of the three-bit control signal enables/disables a set of four fingers, the next most significant bit enables/disables a set of two fingers, while the least significant bit enables/disables one finger. In yet a further refinement, one or more additional fingers are configured to be enabled outside whenever the output driver is activated. Thus, when the counter counts zero, the output driver will have some predetermined minimum number of enabled fingers.